1. Field of the Invention
The present invention relates to a method for improving the reliability of flash memories, and more particularly, to using a HTO film to reduce a random bit failure in a fabricating process to improve the reliability of flash memory.
2. Background of the Invention
For the past few years, there has been an increasing demand for portable electronic products, such as memories for digital cameras, mobile phones, video game apparatuses, personal digital assistants (PDA), MP3 players, etc. Such demand pushes the development of flash memory fabrication technology. Because of its highly reduced weight and physical dimensions compared to magnetic memories, such as hard disk or floppy disk memories, flash memory has a tremendous potential in the consumer electronics market.
Flash memory is typically designed having a stacked-gate or split-gate structure. The stacked-gate comprises a floating gate for storing charges, an oxide-nitride-oxide (ONO) dielectric layer, and a control gate for reading and writing of the data. Like a capacitor storing data, the memory stores charges in the stacked-gate to represent xe2x80x9c1xe2x80x9d data and erases the charges from the stacked-gate to represent xe2x80x9c0xe2x80x9d data. Additionally, the data stored in the memory is renewed through applying an extra energy to the stacked-gate.
Please refer to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 are cross-sectional diagrams of forming a dual-bit stacked-gate flash memory cell according to the prior art. As shown in FIG. 1, a semiconductor wafer 10 comprises a silicon substrate 12, an active area isolated by shallow trench structures 14 positioned on the silicon substrate 12, and two gate structures 24 positioned within the active area on the silicon substrate 12. Each gate structure 24 comprises a gate oxide layer 16 formed on the silicon substrate 12, a polysilicon layer (hereafter referred to as a PL1 layer) 18 positioned on the gate oxide layer 16, and a silicon nitride layer 20 positioned atop the PL1 layer 18. An ion implantation process is performed to implant ions into a region of the surface of the silicon substrate 12 that is not covered by the gate structure 24, i.e. into a bit line region. A thermal oxidation process is then performed to activate the doping ions to form a diffusion layer 22 that serves as a buried drain or source (BD/BS), or a bit line. A thermal oxide layer or BD/BS oxide layer growth step over the diffusion layer 22 then follows.
As shown in FIG. 2, a dielectric layer 26 is formed of silicon oxide on the surface of the semiconductor wafer 10 by performing an HDP CVD (high density plasma chemical vapor deposition) process. The dielectric layer 26 covers the surface of the substrate 12 and the gate structures 24. The top of a region of the dielectric layer 26 covering the substrate is higher than the top of the PL1 layer 18 but lower than the top of the silicon nitride layer 20.
As shown in FIG. 3, a wet etching process is performed with DHF (diluted HF) or BOE (buffered oxide etcher). The dielectric layer 26 is removed in a range of several hundred angstroms to expose the protrusion structure 27.
As shown in FIG. 4, a sacrificial layer 28 is formed of silicon nitride on the surface of the dielectric layer 26 and adjacent to the lateral of silicon nitride 20. Next, as shown in FIG. 5, a CMP (chemical mechanical polishing) process is performed to remove the sacrificial layer 28 and dielectric layer 26 on the silicon nitride 20 to a predetermined thickness. Next, as shown in FIG. 6, the dielectric layer 26 on the silicon nitride is removed. Then a wet etching process is performed with heated phosphoric acid solution to totally remove the sacrificial layer 28 and the silicon nitride 20 on the polysilicon layer 18. A recess 30 is formed with the top of the polysilicon layer 18 and the adjacent dielectric layer 26.
As shown in FIG. 7, a polysilicon layer 32 is formed on the surface of the semiconductor wafer 10 and the recess 30 is filled. The polysilicon layer 32 is electrically connected to the polysilicon layer 18 to form a floating gate of the flash memory. Then a dielectric layer 34 of ONO structure is formed. The dielectric layer 34 comprises a first oxide layer (not shown), a nitride layer (not shown) positioned on the first oxide layer, and a second oxide layer (not shown) positioned on the nitride layer. After that, a polysilicon layer 36 is formed on the semiconductor wafer 10 to cover the dielectric layer 26 and 34 as a control gate of the stacked-gate flash memory cell.
The process in the prior art uses a CMP process to expose the dielectric layer 26 under the sacrificial layer 28 and then remove the sacrificial layer 28 and silicon nitride 20. However, it easily exhibits a problem of excess polishing and leads to low reliability and high costs. Aside from that, while removing the sacrificial layer 28 and silicon nitride 20 with acid solution, the acid solution easily permeats through a seam between the sacrificial layer 28 and the gate structure 24. This randomly occurring acid-corroded seam phenomenon is also called random bit failure.
It is therefore a primary objective of the present invention to provide a method of fabricating a stacked gate of flash memory, especially with a unique HTO film to reduce random bit failure caused by an acid-corroded seam to improve the reliability of the flash memory.
According to the preferred embodiment of the present invention, the method comprises the following steps:(1) providing a substrate that has a channel region and a bit line region on its surface; (2) forming a stacked layer on the substrate in the channel region. The stacked layer comprises a polysilicon layer and a sacrificial layer formed atop the polysilicon layer; (3) oxidizing the stacked layer to create an HTO film on the surface of the polysilicon layer and the surface of the sacrificial layer; (4) depositing a dielectric layer over the HTO film to cover the channel region and the bit line region. The top surface of the dielectric layer on the surface of the substrate is above the top surface of the polysilicon layer and below the top surface of the sacrificial layer; (5) partially removing the dielectric layer and the HTO layer to expose portions of the sacrificial layer; and (6) completely removing the sacrificial layer.
It is an advantage that the present invention reinforces an interface between the dielectric layer and the polysilicon layer to prevent acid-corroded seams being formed during the acid solution dipping process to reduce random bit failure. In addition, when compared with the needed step of performing a CMP process and an additional sacrificial layer in the prior art, the present invention dips the nitride silicon layer directly. The present invention method simplifies the process and improves the reliability of flash memory.